| 摘要 |
PURPOSE:To shorten the executing time of an RR instruction, by skipping an address qualified stage and at the same time starting the decoding of the subsequent instructions at one time in case an instruction (RR instruction) exists between registers following a load/store instruction or a branch success. CONSTITUTION:When a load/store instruction (n) and an RR instruction 16 are consecutive, the instruction (n) is decoded at a stage D and stored to be shifted to a stage A. At the same time, the instruction 16 following the instruction (n) within an instruction buffer register 1 is decoded by a control circuit 3. When the instruction 16 is detected as an RR instruction, the output of the circuit 3 is fed to a latch group 7. The stage A of the instruction 16 is skipped, and a process is carried out at and after the stage B. If a branch succeeds, an instruction is regarded at and after the addresses of a branch destination instruction and the addition of the branch destination instruction address and an RR instruction length. Then the decoding is started for both addresses. |
