发明名称 DIGITAL PHASE CONTROLLER
摘要 PURPOSE:To secure a normal operation by stopping the generation of a firing pulse when a digital input amount is abruptly varied. CONSTITUTION:The output of the first counter which alters its output in response to a synchronizing signal and the output of the second counter which increments the output when the content of the first counter is the prescribed value and increments reversely to the output in response to the generation of a firing pulse are inputted to a comparator 32, which compares these outputs with the set value. When the content of the second counter is the first set value, even if the prescribed large and small magnitude relationship is produced, no firing pulse is generated. A pulse shaping circuit 5 shapes the pulse from a pulse selecting circuit 33, and outputs a pulse of the prescribed time duration.
申请公布号 JPS5889063(A) 申请公布日期 1983.05.27
申请号 JP19810185322 申请日期 1981.11.20
申请人 HITACHI SEISAKUSHO KK 发明人 SHIRAHAMA HIDEFUMI;SUGAWARA SHIYOUICHI;IYOTANI RIYUUJI;KONISHI HIROO
分类号 H02M1/08;(IPC1-7):02M1/08 主分类号 H02M1/08
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