发明名称 SUPERCONDUCTION LOOP LOGICAL CIRCUIT
摘要 PURPOSE:To obtain a superconduction loop logical circuit suitable for circuit integration, by providing a superconduction loop magnetically coupled with input lines and driving a Josephson circuit with an induced current due to an input signal. CONSTITUTION:A superconduction loop 1 has inductances 2-4 of 100pH, input lines 5, 6 are provided in interlinking with the wiring of the said loop 1 and linked to the loop 1 with 90pH of inductance. A gate current is applied from a terminal 9 to a Josephson junction 7 forming a convert circuit together with a load 8 and a bias current is applied from a terminal 10. The junction 7 is driven via the loop 1 through the presence/absence of the current of the input lines 5, 6 and in case of the circuit shown in figure, it has a function of an AND circuit. Various logical circuits can be constituted by changing the linking method between the input lines and the superconduction loop in this invention.
申请公布号 JPS5888933(A) 申请公布日期 1983.05.27
申请号 JP19810187027 申请日期 1981.11.24
申请人 HITACHI SEISAKUSHO KK 发明人 ASANO JIYUNSHI
分类号 H01L39/22;H03K19/195 主分类号 H01L39/22
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