| 摘要 |
PURPOSE:To prevent erroneous display and to display a stable focus adjustment state by adding simple logic and inhibiting held data from being updated unless the focus adjustment state is detected. CONSTITUTION:A signal 24 which has a high level when the focusing state of a focusing detector is detected and the output 23 of an AND gate 22 which generates a high-level pulse in only one clock when a decision on the focusing state is decided are ANDed by an AND gate 28 to generate the decision completion pulse of a focusing state decision making circuit at the output 29 of the gate when external conditions are normal. When the focus adjustment state is not detected, an AND gate 33 cuts off transmission to the output 29 and AND gates 4 and 8 are turned off to held inputs to D-FFs 6 and 10 at a level L, obtaining a code corresponding to the state that a state decision can not be made. Thus, held data is not updated, so erroneous display is prevented to display a stable focus adjustment state. |
