| 摘要 |
PURPOSE:To attain frequency division with highly effective accuracy, by summing oscillation frequency deciding inputs at each clock input, counting an overflow signal and summing to the higher-order. CONSTITUTION:An accumulator 2 sums an input value for oscillation frequency decision and a value of a register 3 at each clock input and stores the result in the register 3 again. When the accumulator 2 is overflowed, a counter 4 counts it. The linking between the count result and the content of the register 3 is equivalent to the extension of the number of bits of registers and accumulators, and since the accumulation is shifted right with a shifter 5 for the division, the repetitive period with high accuracy can be obtained. |
