| 摘要 |
PURPOSE:To reduce the wiring region required for the wiring to be formed between blocks by a method wherein the position of the outer terminal of the blocks is provided on the upper and the lower sides of the column of cells in the blocks, and the depletion region in the blocks is used for the interblock wiring to be performed between the blocks. CONSTITUTION:The internal wiring region 3 on a master slice LSI substrate 1 has a cell alloy, whereon a cell 4 was provided in the n row of the m column, and a wiring region 5 between the cell column 6, and also the cell 4 is constructed in such a manner that a transistor and a resistor are electrically isolated with each other. The blocks 7 and 8 provided in the inner wiring region 3 consist of the cell 4, interconnected wirings 70 and 80 located between cells, and outer terminals 71, 72 and 81-83. In the blocks 7 and 8, the outer terminals 71, 72 and 81-83 are provided on the upper and the lower sides of the cell column 6 located in the block. As the position of the outer terminal in the block is provided on the upper and the lower sides of the cell column as above-mentioned, the wiring region required for the wiring to be performed between the blocks can be reduced. |
