| 摘要 |
PURPOSE:To provide clock information for serial signals, to make bit synchronism easy and to detect line interruption, by modulating in terms of pulse width the serial signals subjected to parallel-serial conversion, in a time division multiplex communication system. CONSTITUTION:Parallel input data D-1-D-n are multiplexed in time division into a serial signal (d) with a clock pulse (a), sampling pulse (b) and frame pulse (c) being outputs of a timing forming device 1. The serial signal (d) is modulated in terms of pulse width into a signal (e) with a pulse width modulating circuit 3 and transmitted to a transmission section B. The reception signal (e) is serial/ parallel-converted at a serial-parallel converter 5 with a clock (f) extracted from a clock extracting circuit 4 and held at a holding circuit 8. A reception timing forming device 6 detects a frame signal of a reception signal, forms a syncrhonizing signal (h), establishes the synchronism of the holding circuit 8 and obtains data D-1'-D'n'. |
