| 摘要 |
PURPOSE:To obtain a digital/analog converter through PWM conversion through which the clock frequency can be decreased without reduced resolution, by combining outputs of a plurality of the PWM converting means with weighting. CONSTITUTION:Inputted digital signals are grouped (101-108 and 109-116), they are converted into a PWM signal on each group (set of 11, 13, 15, 21 and set of 10, 12, 14, 21), different amplitude is given to PWM signals (i), (e) (17,18, 19, 20), and each PWM signal provided with different amplitude is formed into a prescribed order (a, f) and passes through a low-pass filter 9 in time series to output an analog signal (e), allowing to decrease the clock frequency (b) without decreasing the resolution. |
