| 摘要 |
PURPOSE:To effectively improve a latchup withstand amount without loss of economy by simultaneously forming P<-> type diffused layers at the periphery adjacent to a P<-> type well around the well. CONSTITUTION:P<-> type layers 61 are simultaneously formed adjacent to the periphery of a P<-> type well 62 around the well. When a positive polarity noise is applied to the terminal 1N of a C-MOSIC, a hole 70 is injected, but the periphery of the P<-> type well 77a is ground potential, the hole is preferentially collected to a deep P<-> type layer 77b formed simultaneously upon the well 77a, and does not arrive at the well 77a. In other words, since it is equal to the P<-> type collector ground of a pnp type element in an equivalent manner and no SCR operation occurs, its latchup withstand amount can be remarkably improved. Further, the width of the layer 61 may be in narrow width without loss of the economy of the chip area since part of a surge is flowed to the ground electrode, and when a P<+> type layer is superposed on the layer 61 or metallic wirings are superposed on the layer 61, an effect of reducing the lateral resistance of the P<-> type layer can be further performed. This configuration is effective in case that a latchup inducing noise is applied to the output terminal, and is effective against both positive and negative polarity noises. |
