| 摘要 |
PURPOSE:To improve use efficiency of a file device by varying the assignment rate of the usable time of a file device in accordance with the file access requesting degree of individual processors. CONSTITUTION:When processors 2, 4 and 3 all attain access, a register 8 is given logic 11 and latches input states supplied to input terminals I1 and I2 by clock pulses CP, and obtains logic 11 at output terminals O1 and O2. On the other hand, logic levels 1 and 0 are obtained alternately at the output terminal of a counter 7 every time the pulse CP is generated, and logical levels 111 and 110 are obtained alternately at input terminals A2, A1, and A0 of an ROM9. As a result, logical levels 1 and 0 appear at the output terminals of the ROM9 alternately. Therefore, a selector 6 couples processors 2 and 3 with a file device 1 alternately every time the pulse CP is generated. |
