发明名称 Method and apparatus for testing an integrated circuit
摘要 In order to set the circuit to be tested to a test mode, at least one output is led out by an output stage, and the input and output of the output stage internally leads to an exclusive-OR gate. As long as the output has a comparatively high-ohmic termination, as is the case during the normal mode of operation, the exclusive-OR gate will carry the same signal for both signal conditions of the output. For the purpose of testing a complementary pulse pattern is applied to the output, so that the exclusive-OR gate supplies an opposite signal, which establishes the test mode. The output of the exclusive-OR gate may lead to a bistable multivibrator, so that for establishing the test mode only a single complementary signal is required.
申请公布号 US4385275(A) 申请公布日期 1983.05.24
申请号 US19800142293 申请日期 1980.04.21
申请人 U.S. PHILIPS CORPORATION 发明人 DELVIGNE, JOSEPHUS
分类号 G01R31/28;G01R31/317;G01R31/3185;(IPC1-7):G01R15/12 主分类号 G01R31/28
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