发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To speed up data transfer by providing a strobe means which selects a memory device and a peripheral device at the same time and places them in reverse operation states, and disconnecting a data bus from a CPU when they are selected. CONSTITUTION:When an address recorder 5 selects a memory device 3 (or peripheral device 4), the peripheral device 4 (or memory device 3) is selected at the same time. A bus buffer 6 disconnects a data bus DB from a CPU side 1 in two ways when the memory device 3 and peripheral device 4 are selected. The bus buffer 6 sends data from the memory device side 3 to the CPU side 3 when a read strobe RD outputted from the CPU1 is ''1'', or from the CPU side 1 to the memory device side 3 when the read strobe RD is ''0''. The peripheral device 4 connects with a signal line for the write strobe WR of the CPU and a signal line for the read strobe RD in reverse relation.
申请公布号 JPS5886623(A) 申请公布日期 1983.05.24
申请号 JP19810184142 申请日期 1981.11.17
申请人 RICOH KK 发明人 YAMAGUCHI SHINGO
分类号 G06F13/36;G06F12/00;G06F12/06;G06F13/28;G06F13/42 主分类号 G06F13/36
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