发明名称 INTEGRATED CIRCUIT FOR CONTROL OF MEMORY
摘要 PURPOSE:To ensure proper interleave action, by applying a memory access request signal to an address transfer means selectively but not simultaneously. CONSTITUTION:A selecting circuit (f) is separated from the side of a basic circuit (d)-1 with the acceptance signal produced from the circuit (d)-1 and then selects the side of a basic circuit (d)-2. Then the circuit (f) connects the memory access request signal RQ to the side of the circuit (d)-2. The next memory access is given to the circuit (d)-2. If the memory block address which is designated by the memory access request is not registered to a present memory block register 2, that is, the designated memory block is not under the memory access, the memory access request is immediately accepted at the side of the circuit (d)-2. Then the requested memory access is started.
申请公布号 JPS5884355(A) 申请公布日期 1983.05.20
申请号 JP19810183305 申请日期 1981.11.16
申请人 NIPPON DENKI KK 发明人 KOBAYASHI HIDEHIKO
分类号 G06F12/00;G06F12/06 主分类号 G06F12/00
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