发明名称 CONNECTING METHOD FOR INTER-ELEMENT WIRING
摘要 PURPOSE:To perform the perfect etching removal of the unnecessary part of metal for wiring adhered later, then the formation of fine wirings without short- circuit in the same layer and the improvement of the yield, by forming a flat protection film on the wiring unnecessary part. CONSTITUTION:An insulating film 43 of CVD-SiO2, P-CVD-SiN, etc. is adhered on the surfaces of a semiconductor substrate 41 and semiconductor elements, and holes 44 for connection with the element are opened by an etching. Next, to change the surface into flatness, e.g. photo resist, polyimide as the protection film 45 is adhered flat over the entire surface to the thickness of approx. 1- 10mum resulting of the formation of a protection layer A. Even when the surface of the insulating film 43 has projections of approx. 1-5mum and reverse tropoidal sections, the protection film 45 becomes a sufficiently flat surface. Next, the photo resist 47 covering the wiring region is formed by a photo process resulting in a protection layer B. Thereat, an unnecessary metallic region is perfectly removed because of flat formation, and the short-circuit in the same wiring layer is not generated.
申请公布号 JPS5884447(A) 申请公布日期 1983.05.20
申请号 JP19810182330 申请日期 1981.11.16
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 ASAI KAZUYOSHI;KURUMADA KATSUHIKO
分类号 H01L21/3205;H01L21/306;H01L21/3213 主分类号 H01L21/3205
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