| 摘要 |
PURPOSE:To decrease the number of required elements, by using a flip-flop circuit controlling clock signals supplied to a transfer gate depending on the state of input. CONSTITUTION:When an input Dn is ''H'', a clock -CK' is given to an AND circuit AND11 to invert an output Qn via transfer gates TG11, TG12 and inverters I11-I13. When the input Dn is ''L'', a clock signal being the -CK' is stopped to hold the output Qn. As a result, the input signals can be frequency-divided by a half with less number of elements. In constituting an n-frequency division circuit concretely, the number of gates can be decreased from the conventional numbers of 7Xn into 6X(n+1). |
