DERIVING CLOCK SIGNAL FROM RECEIVED DIGITAL SIGNAL

摘要

An arrangement for deriving a clock signal from a received signal which has been digitally processed in a processing circuit (72) and is available only as a sampled signal at discrete time intervals comprises first and second sample and hold circuits (73, 75) which sample the signal at a multiple of the bit rate so that at least some of the samples are taken at intervals which correspond to nominal zero crossings. A steering circuit (81) driven by a decision circuit (80) determines which of the circuits (73, 75) samples the input signal depending on whether a transition is enclosed by a (1,0) sequence or a (0,1) sequence. The outputs of the sample and hold circuits produce an error signal which is used to control the frequency of an oscillator (78) which drives a timing generator (79). The timing generator (79) controls the instants at which the input signal is sampled both within the processing circuit (72) and by the sample and hold circuits (73, 75). An inverter (74) is connected to the input of the sample and hold circuit (75) to enable the same polarity output to be given to a phase retarded signal regardless of the direction of the zero crossing transition.