| 摘要 |
PURPOSE:To attain a tri-state level clock generator which is operated in an integrated circuit of a single power supply operation and has a polarity inverted to that of a power supply voltage, by providing a capacitor respectively coupling the gate and output terminal of the 1st and 2nd MOSFETs. CONSTITUTION:The drain of an MOSFETQ1 is connected to the 1st power supply line VDD, the source is connected to an output terminal N1, and the drain of an MOSFETQ2 is connected to the terminal N1, and the source is connected to the 2nd power supply line GND. The 1st coupling capacitor C1 is connected between the terminal N1 and the capacitance coupling clock line theta1. The 2nd and 3rd coupling capacitors are connected between the gates of the FETQ1, Q2 and the terminal N1. Clock signals which take the voltage level of the opposite polarity as the voltage of the VDD viewed from the GND and that of the GND as a binary level are given to the gates of the FETs Q1, Q2. |
