| 摘要 |
The frequency comparator circuit serves to determine whether the signal received contains an expected signal of frequency f and time B. After clipping, the signal received is used as the logic signal A for comparison with two square-wave signals F and Fq in quadrature and of frequency f. Two counters count forwards respectively when AFFq U AFFq=1 and AFFq U AFFq=1 and count backwards when AFFq u AFFq=1 and AFFq U AFFq=1. The passage of the counters through predetermined counts indicates that the expected signal has been received. In order to reduce errors and obtain a maximum count with the expected signal, a control device incorporating a delay circuit only authorises the operation of the counters when A and A delayed by K/f differ, with K such that K/f</=B<K+1/f. |
