| 发明名称 |
MOS Transistor circuit with a power-down function |
| 摘要 |
An MOS transistor circuit contains at least one "zero" threshold mode transistor to provide a power-down function for the circuit. The "zero" threshold mode transistor is connected between an enhancement-mode MOS driver transistor and a depletion-mode MOS load transistor.
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| 申请公布号 |
US4384220(A) |
申请公布日期 |
1983.05.17 |
| 申请号 |
US19810229746 |
申请日期 |
1981.01.29 |
| 申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
SEGAWA, MAKOTO;ARIIZUMI, SHOJI |
| 分类号 |
G11C11/41;G11C11/407;H01L21/822;H01L27/04;H01L29/78;H03K19/00;H03K19/0185;H03K19/0944;H03K19/096;(IPC1-7):H03K17/68;H03K19/09;H03K19/20 |
主分类号 |
G11C11/41 |
| 代理机构 |
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代理人 |
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