发明名称 BUS CONTROLLER
摘要 PURPOSE:To prevent a bank of a memory from having unnecessary idle time, by providing a busy line for sending a sinal showing that a bank of the memory device is in operation in the time slot after next. CONSTITUTION:A basic processor 1, channel controller 2, and main memory device 3 are used by a bus 4 on time-division basis. For this purpose, bank next busy lines 16 and 17 are provided to transmit signals showing that banks 5 and 6 of the memory device 3 are in operation in the time slot after next. On confirming the signal from the busy lines 16 and 17, a device which is to access the banks among plural device sends out an access request signal to its bus request line.
申请公布号 JPS5882327(A) 申请公布日期 1983.05.17
申请号 JP19810180623 申请日期 1981.11.11
申请人 MITSUBISHI DENKI KK 发明人 NAKAMURA SHIYUNICHIROU
分类号 G06F13/362;G06F12/00;G06F13/16;G06F13/18 主分类号 G06F13/362
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