| 摘要 |
PURPOSE:To eliminate the need for a 3dBPCM attenuator, to reduce power consumption and hardware in size, and to shorten delay time, by allowing a mu rule bias correction part and a segment update part in a mu rule PCM code direct adder to include a 3dB attenuating function. CONSTITUTION:A linear absolute-value adder and subtracter 4 performs linear absolute value addition or subtraction according to the specification of a mu rule bias correction part 2, and the result is sent to a shift register 5 and a segment variation part 6. The variation part 6 varies a large segment (f) from an absolute value comparison part 1 according to the result of said adder and subtracter 4, and subtracts 1 for 3dB attenuation. The output of the adder and subtracter 4, on the other hand, is supplied to the register 5, and shifted to obtain a mu rule PCM code type, thereby obtaining an output OUT from the polarity bit of a large absolute value side, the output of the update part 6, and the output of the register 5. |
