发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To perform efficient memory control over pattern data, by selecting a memory circuit according to a changeover flag bit added to the head or tail of data, and outputting pattern data consisting of different-bit-length data in combination. CONSTITUTION:When a control part 1 performs access to a memory circuit 3a through an address circuit 2a firstly to output one pattern, a switching circuit 5 sends a signal to a selecting circuit 4, and a gate A selects readout data from a memory circuit 3a to obtain an output signal. In this case, the selecting circuit 4 and address circuits 2a and 3b are switched according to flag bits added to memory circuits 3a and 3b to sent contents out of the memory circuits 3a and 3b, so that pattern data is outputted from the selecting circuit 4 automatically.
申请公布号 JPS5882345(A) 申请公布日期 1983.05.17
申请号 JP19810180538 申请日期 1981.11.11
申请人 FUJITSU KK 发明人 KANEKO AKIRA
分类号 G06F11/22;G06F11/263;G11C29/10;G11C29/56 主分类号 G06F11/22
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