| 摘要 |
<p>PURPOSE:To measuring the phase of a logical element at its clock terminal indirectly at a high precision level, and to allow adjustment by returning a supply clock to a phase detecting circuit provided separately from a load circuit. CONSTITUTION:A phase adjusting circuit 21 receives a signal from a clock generator 1 to send out clocks phase-adjusted in correspondence to load circuits 31-31a, which have auxiliary delay elements having delay time twice as long as clock delay time between clock input terminals A2-N2, and clock feedback terminals A4-N4. Difference signals between clock delay time signals from output terminals A4-N4 of the circuit 21 and preset reference delay time are sent from a phase detecting circuit 5 to the circuit 21 to perform phase adjustment of the clock delay time, thus indirectly adjusting clock delay time at the clock terminal of a logical element.</p> |
