| 摘要 |
PURPOSE:To obtain a memory which can have a simultaneous access through plural series and contains plural data buses and address buses, by connecting an even number of unit circuits constituted by combining NOT logic elements and transmission gates. CONSTITUTION:A unit circuit is provided with the 1st terminals 16 and 26 connected to a writing bus, the 2nd terminals 17 and 27 connected to a reading bus, input terminals 11 and 21, output terminals 12 and 22, the 1st transmission gates 15 and 25 connected in series between the input and output terminals, NOT logic elements 1 and 2, the 2nd transmission gates 13 and 23 connected between the 1st terminals and the joints of the 1st transmission gates and the NOT logic elements, and the 3rd transmission gates 14 and 24 between the 2nd terminals and the output terminals. The input terminals are connected to the output terminals of an even number of unit circuits to each other. Thus a closed circuit is obtained. As a result, a simultaneous access is possible through plural series. |
