| 摘要 |
PURPOSE:To attain mangification and shrinkage with a wide range, by providing a fraction adder summing lower-order bits of a shift register storing outputs through the use of a multiplier multiplying input image data by P and an output adder for run length signals and controlling the both. CONSTITUTION:A decoder 1 decodes a makeup code and a terminate code of the modified Haffmann code serially inputted and sets them to a register 11. A multiplier 2 multiplies the content of the register 11 with a value P stored in a register 12. A shift control 3 controls each bit of the register 14. A lower-order 6-bit of the register 14 is inputted to an adder 4 and set to a register 15 storing the preceding integrated value through addition. A carry output sets a carry storage register 16. An AND gate 6 inputs an output of the register 16 and an input of a signal line 102 and the output of an output adder 5. The adder 5 outputs the result of addition of an output value of the gate 6 to the output of the register 14 as a run length. |
