| 摘要 |
The apparatus determines the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with a number of identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbour processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array of processors may be utilized to wire a much larger array of cells. The arrangement gives reduced design times. |
