| 摘要 |
PURPOSE:To reduce the occupied area in forming a counter having many stages on an LSI chip, by making the circuit constitution of each stage equal to each other, in an up-down counter constituted through the connection of filp-flops of multistages. CONSTITUTION:When the logic of an up-down switching signal 1 is 0, an output of an NOT circuit 54 is 1, when a signal 80 representing the input from a low- order digit and a Q output of a D flip-flop 28 are both 1. An output of an NOT circuit 55 is 1, when an output of the NOT circuit 54 and a Q output of a flip- flop 29 are both 1. Thus, in this case, a counter executes up-count at each input of a count signal 4. In taking the logic of the switching signal as 1, the output of the NOT circuit 54 is 1 when the Q output of the flip-flop 8 is 0 and the signal 80 is 1, and the output of the NOT circuit 55 is 1, when the output of the NOT circuit 54 is 1 and the Q output of the flip-flop 29 is 0. Thus, the counter consisting of the flip-flops 28-30 down-counts at each input of the signal 4. |
