| 摘要 |
PURPOSE:To reduce troubles to be applied to a control system at the quick variation of an output of a controller by forming a primary delay signal on the basis of the output signal of the controller and limiting the output signal of the controller within the amplitude of a signal converted by adding or subtracting a constant signal to/from the delay signal. CONSTITUTION:A signal converting circuitIand an intermediate value signal selecting circuit II as an amplitude limiting circuit are connected to the output terminal P1 of an analog control unit ACU. In the circuitI, an integration circuit consisting of a resistor R1 and a capacitor C1 and an operational amplifier OA1 are connected in series to form a primary delay signal Le1. A voltage dividing resister R2 divides the voltage of a constant voltage source to form a voltage dividing signal (ep). Operational amplifiers OA2, OA3 adds and subtracts the signal (ep) to/from the signal Le1 respectively to fetch signals E1, E2. In the circuit II, an output signal E3 from the control unit ACU is limited within the amplitude of the signals E1, E2 by operational amplifiers OA4-OA6 and outputted as a control signal of a process controlling system through a operational amplifier OA7. |
