| 摘要 |
<p>A TV timebase circuit includes a vertical sync counter in the form of a ten-bit ripple-through counter (60). Additional logic circuitry including a pair of divide-by-four counters (93, 95), a latch (94), a D flip-flop (55), and associated AND (81, 82, 83, 85, 87 and 90), NAND (84, 86, 88, 89 and 92), and inverter gates (40, 42, 43 and 45) are also provided. The circuit is responsive to a multiple of the horizontal frequency and to vertical sync pulses and is capable of automatic recognition of 525 or 625 line standard. The logic includes a mechanism for locking out the vertical counter's 525 count when operating in the 625 mode. The latch (94), in association with one of the divide-by-four counters (93, 95) serves a "fly wheel" sync function, whereby a predetermined number of "matches" must be recognized to lock the circuit into a given mode, and whereby a predetermined number of "mis-matches" must occur to drop the circuit operation from the locked-in mode. Several outputs are taken off the vertical counter (60) to operate ramp drive and blanking functions of the TV vertical sweep generator. An output representative of the particular line standard being decoded may be used to provide chrominance decoding information and picture height control information.</p> |
