发明名称 OUTPUT CIRCUIT FOR TRANSISTOR TRANSISTOR LOGIC CIRCUIT
摘要 PURPOSE:To make the shoulder part of the leading edge of an output signal waveform steep by discharging an electric charge stored in a collector-base capacitance of an output transistor (TR) while the leading edge of the output signal is detected to eliminate the mirror effect. CONSTITUTION:A TR Q2 is conducted through the conduction of a TR Q1 with a terminal 10 at 'H' level, TRs Q3, Q4 being active loads are cut off and the level of a terminal 11 goes to L. The electric charge is stored in the collector-base capacitance of the TR Q2 in such a case. With the level of the terminal 10 at L level next, the TR Q1 is cut off and the TRs Q3, Q4 are conducted and the potential at the terminal 11 rises. Thus, the collector-base capacitance of a TR Q5 is charged rapidly and the TR Q5 is conducted. Then the TR Q5 detects the leading edge of the signal waveform at the terminal 11 to transfer it to a TR Q6. Through the electrification of the TR Q6, the charge stored in the collector-base capacitance of the TR Q2 is discharged rapidly. Thus, the shoulder of the leading edge of the output signal is made steep without the mirror effect of the TR Q2.
申请公布号 JPS639227(A) 申请公布日期 1988.01.14
申请号 JP19860152939 申请日期 1986.06.30
申请人 FUJITSU LTD 发明人 YOKOTA NOBORU;MATSUDA HIROYUKI
分类号 H03K17/04;H03K19/013;H03K19/088 主分类号 H03K17/04
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