| 摘要 |
An automatic measurement data (test data) synchronisation device which consists in a known manner essentially of a transmitting register, a synchronisation register and a receiving comparison register, is intended to differentiate between asynchronism of normal bit error periodicities and to be capable of operation at the very high bit rate which can be achieved by the respectively available chip family. According to the invention, the EXOR gates which are required for feeding back the registers are constructed from parallel shift registers (27 in Fig. 4) using their dynamically driven shift/load (S/L) changeover switching inputs. The number of positions of the registers is changed over in order to change over the bit pattern. This is achieved according to the invention by statically driving the S/L changeover switching inputs of the parallel shift registers (29, 31 and 33). During asynchronous operation, the signal "load registers" at the S/L changeover switching input of the second parallel shift register (28) of the receiving comparison register causes the received measurement data (QZF) to be read in in serial form into this receiving comparison register. <IMAGE>
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