发明名称 FAILURE ANALYZING DEVICE FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To make failure analysis more accurate and highly efficient, by a method wherein quality is inspected by moving an IC to a predetermined position on the basis of the logical circuit diagram data and mounting data. CONSTITUTION:A logical circuit diagram data for an IC 8 to be inspected is read out from a memory 2 by a central processing unit 1 and displayed 4, and a specific area is designated by a cursor. The specified data is read into a controller 1 by the coordinates of the specified data on the display 4 and the page number of the logical circuit data, then the selected circuit is judged. The layout information is read out to the CPU 1 from the memory 3 to obtain the position thereof in a chip, and the drive is controlled 6 so that an XY table 7 coincides with this posision. The IC 8 is made operative by a driving circuit 5 and irradiated by an electron beam 14 to detect 9 a secondary electron 15 corresponding to the quality of the logical circuit under operation. The detected output is given to a monitor 10 as an accurate signal in synchronizm with a deflecting scan of the beam, and displayed. Thus the operating state of the IC is clarified and the failure analysis can be speedily carried out.
申请公布号 JPS5870541(A) 申请公布日期 1983.04.27
申请号 JP19810168840 申请日期 1981.10.23
申请人 FUJITSU KK 发明人 GOTOU YOSHIAKI;ITOU AKIO;FURUKAWA YASUO
分类号 G01R31/28;G01R31/302;H01J37/28;H01L21/66 主分类号 G01R31/28
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