| 摘要 |
PURPOSE:To obtain a frequency multiplication circuit of no adjustment, suitable for circuit integration with high accuracy, by delaying an input signal through the drive of a shift register with a clock being an integer multiple of a carrier frequency of the input signal and taking exclusive logical sum between the delayed signal and the input signal. CONSTITUTION:A modulation signal input is converted into a rectangular wave signal A at a voltage comparison circuit 10 via a coupling capacitor 11, the signal A is inputted to a shift register 290 of 2n-stage operated with a clock signal T, 8n times the carrier frequency, and a signal AD delayed by pi/2 radian in terms of the phase angle of the carrier wave. The output of the shift register 290 is inputted to an exclusive logical sum circuit 294 with the input signal A and a two-multiplicated output C appears at the output. |
