Synchronously operatable PCM recording processor

摘要

A PCM recording processor which is synchronously operatable is disclosed. Two kinds of clock signals and two kinds of synchronizing signals enable two PCM recording processors to operate so as to be synchronized with each other. One master mode processor sends signals to plural slave mode processors through bi-directional input/output ports. These two modes are easily switchable. The synchronizing signals are generated by AND-gating each output of asynchronously cascaded counters in the timing generators in a PCM recording processor. A counter in the first stage of the cascaded counters is synchronously reset by the synchronizing signal and the other counters in the following stages are asynchronously reset by a delayed synchronizing signal in the slave mode processor.