| 摘要 |
<p>PURPOSE:To shorten the clock interruption processing time of each computer system by externally supplying computer systems with a clock frequency-divided according to a control period. CONSTITUTION:A master clock signal MCLK from a master clock signal generator 2 is supplied to computer systems 1a, 1b, and 1c through clock controllers 4a, 4b, and 4c. The clock controller 4a (4b and 4c) has its RS flip-flop 5 set by a start command signal STRT from an external sequencer 3 and reset by a stop command signal STP to decide on whether the MCLK is supplied to the computer system or not. When the flip-flop 5 is set, the MCLK is frequency- divided by a frequency divider 7, and the resulting signal is supplied as the control period synchronizing clock to each computer system. Thus, interruption judgement processing time is shortened.</p> |
