发明名称 MULTI-LAYER WIRING CIRCUIT
摘要 <p>PURPOSE:To raise the yield of a multi-layer wiring circuit by altenately lengthening the terminals of the signal lines of an upper layer wiring line constituting a matrix multi-layer wiring circuit for selectively supplying information to heating elements. CONSTITUTION:The lengths of lines at the terminals of a wiring line are varied in an extent to which short-circuit does not occur between the wiring lines due to soldering by deforming the shape of the terminals of the wiring lines into different lengths (uneven height) for every line arranged at equal pitches. Thus, the thickness of a Cu solder layering formed by an electric plating method can be increased, the resistance value of the wiring line can be reduced, and the heat efficiency can be raised. Also, the yield of forming a multi-layer wiring circuit can be greatly improved.</p>
申请公布号 JPS5867475(A) 申请公布日期 1983.04.22
申请号 JP19810165756 申请日期 1981.10.19
申请人 HITACHI SEISAKUSHO KK 发明人 YABUSHITA AKIRA;KAWAHITO MICHIYOSHI;MITANI MASAO
分类号 H05K3/46;B41J2/345;H01L49/00;H01L49/02 主分类号 H05K3/46
代理机构 代理人
主权项
地址
您可能感兴趣的专利