| 摘要 |
PURPOSE:To realize the simplification and flexibility of a signal collating circuit, by setting the clock period of a shift register at the value corresponding to the frequency necessary to regard as an effective signal and using the output signal to a logical arithmetic output of plural shift registers. CONSTITUTION:The value of a receiving signal 10 is shifted successively from an output 31 to an output 34 of a shift register on the basis of a clock signal 40. The period of the signal 40 is set at the value corresponding to an input frequency necessary to regard the signal 10 as an effective signal. The 2nd stage output 32 and an output 35 of a NOT input AND element 22 are led to a reset input. Then outputs 31-34 are all reset when both the signal 10 and the 2nd stage output 32 are set at 0. On the other hand, an OR is secured by an OR element 23 between the output 32 and the 4th stage output 34. Then a ''1'' signal is delivered as an output signal 20 of a signal collating circuit when the output of either stage is set at ''1''. |
