| 摘要 |
PURPOSE:To accomplish the small-sized cell, to sharply increase the number of wiring channels and to contrive reduction in size of the chip for the titled device by a method wherein the pitch of a gate electrode, which controls the pitch of wirings in cells, is reduced by properly bending the gate electrode in the vicinity of a connection hole, and said pitch is coincided with the system wiring pitch. CONSTITUTION:A logical block 1 is located on an Si chip 2, and each block 1 is connected by a polycrystalline Al wirings Al1 and Al2. The block 1 itself has a row of unit cells 5 between power source lines 3 and 4, and the row of cells is connected by a polycrystalline SiPS and Al1 and Al2. The connection holes 16- 25 of the Al wirings 11-15, for the P<+> layer 9 and N<+> layer 10 of MOSFET7 which constitutes the cell 5, are formed. At this time, the holes 16-19 and 22- 25 are arranged under a predetermined regularity at the upper and the lower parts, and gate electrodes PS1-PS5 are bent, as occasion demands, approximately 45 deg. in the vicinity of the connector holes. If the positions of the holes and the gate electrodes are properly selected at various places, the gate terminals A-E and A'-E' can be coincided with the system wiring pitch while the gate electrode intervals are being reduced. |
