| 摘要 |
PURPOSE:To provide IC containing the power supply function in itself and having unit cell being suitable for automatic wiring, by a method wherein power supply region for a substrate and well potential is formed near source or drain of MOSFET constituting the unit cell and connected with wiring in the cell. CONSTITUTION:Logic blocks 1 on Si chip 2 are mutually connected by multiple- layer wirings Al1, Al2, and the block 1 itself has a unit cell 5 between power source lines 3, 4. In FET7 within the cell a power source wiring 11 is formed to N<+> layer 28 contacting P<+> layer 9, and VDD is supplied to a layer 9 through a connecting hole 16. A substrate 6 is supplied with power from the N<+> layer 28 through a hole 34. In FET8 three P<+> layers 30 contacting N<+> layer 10 are formed to P<-> well 29, and ground potential is supplied from wiring 12 through holes 35-37 arranged corresponding to system wiring pitch. Connecting holes 16-25 between the layers 9, 10 and Al wirings are arranged according to regular rule, and gate electrodes PS1-PS5 are bent near holes if necessary. In this constitution the cell size can be reduced and the local latch up is not produced. |
