发明名称 |
Frequency synthesizer of the phase lock loop type |
摘要 |
In a phase lock loop frequency synthesizer, a successive addition rate multiplier provides a correction signal for eliminating ripple in a frequency control signal applied to a variable frequency oscillator which produces the output frequency of the synthesizer. Ripple elimination is improved by means of a feedback loop by which any residual ripple is detected and the correction signal is automatically adjusted.
|
申请公布号 |
US4380743(A) |
申请公布日期 |
1983.04.19 |
申请号 |
US19810226326 |
申请日期 |
1981.01.19 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
UNDERHILL, MICHAEL J.;WALTERS, NIGEL J. |
分类号 |
H03L7/18;H03L7/081;H03L7/187;H03L7/197;(IPC1-7):H03L7/18 |
主分类号 |
H03L7/18 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|