| 摘要 |
<p>A delay circuit comprising a counter, a flip-flop circuit, a circuit for holding them to their reset conditions during presence of a first signal and a gate circuit having a second signal on its input and put to ON and OFF by the output from the flip-flop circuit, can provide in a digital manner a relatively long delay time from the end of the first signal to the stop of the output of the second signal and with ease even designed as an integrated circuit. The delay circuit is suitable to be used in a tuning ciruit of an electronic tuning type ratio receiver.</p> |
