| 摘要 |
PURPOSE:To correctly fetch data even at supplementing synchronizing signals, by outputting a synchronizing signal detection pulse to the center of a range without level fluctuation at the back side of a synchronizing signal pattern and determining the reference of data fetch timing. CONSTITUTION:When a synchronizing signal (b) inputs to a terminal 1, the level inversion of the signal (b) is detected at shift registers SR2A, 2B and an EOR circuit 3 to output a pulse (c). A synchronism detecting circuit 4 detects a prescribed time interval from the signal (c) and outputs a synchronizing pulse (c). The signal (d) is delayed 6 and located at almost the center of the back side of a synchronizing signal pattern to become a signal (e) and to reset an FF8. The time of an output of the FF8 is adjusted at SR9A, 9B, an inverter 10, and an AND circuit 11 and a timing pulse (h) between the detection of the synchronizing signal and the incoming of the 1st data is outputted to an FF12. An output of the FF12 opens a gate 13 and applies a signal (i) to a data fetching circuit 16. The missing of the synchronizing signal is detected at a synchronism supplementing circuit 5 and the supplemented pulse is outputted to the location of the pulse (h). |
