发明名称 DIGITAL SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To improve follow-up properties with respect to time axis fluctuation of input data, by using an edge signal and a specific pattern extracting signal of an input digital signal in common and regarding them as a synchronizing signal for a start-stop synchronizing circuit. CONSTITUTION:An input digital signal 1 is inputted to an edge detection circuit 2 and a specific pattern extracting circuit 4 to produce an edge signal 3 and a pattern extracting signal 5. An output signal 9 of a frequency oscillating circuit 8 is inputted to a frequency division circuit 10 for 1/N frequency-division, the output signal is inputted to a decoder 12 and a time gate window signal 13 is produced. The edge signal 3 is a pulse having 1/8 edge interval T of the signal 1, the window signal 13 is a signal having 3/8T, and the edge signal 3 located at the window signal 13 becomes an output signal 15 of an AND gate 14, the frequency dividing ratio of the circuit 10 is controlled with a logical sum signal 7 between the signals 15 and 5 to match the phase of a discrimination window signal 11 for signal discrimination. Thus, even if the time axis of the signal 1 is greatly fluctuated, synchronism can be attained.</p>
申请公布号 JPS5864842(A) 申请公布日期 1983.04.18
申请号 JP19810162836 申请日期 1981.10.14
申请人 HITACHI SEISAKUSHO KK 发明人 ARAI TAKAO;OOKUBO EIJI;ENDOU HIROSHI;KOBAYASHI MASAHARU;TAKEUCHI TAKASHI
分类号 H04L7/04;G11B20/14;H04L7/08;(IPC1-7):04L7/08 主分类号 H04L7/04
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