| 摘要 |
PURPOSE:To perform subminiaturization, high integration, and an increase in capacity, by providing the 1st FET, 2nd FET, capacitance between the gate electrode of the 2nd FET and the 2nd electrode, a digit line, a write address line, and a read address line. CONSTITUTION:The P area 103 of a P channel MOST and the P gate 105 of an N channel JFET float electrically to form a charge storage area and capacitance 109 connected to it is charged and discharged to store binary information. For writing, a write address line 112 connecting with the gate 101 of the MOST and a digit line 111 connecting with the N area 108 of the JFET are held at a prescribed voltage to turn on the MOST. For reading, the digit line 111 is connected to a sense amplifier, and a read address line 113 connecting with the N area 107 of the JFET through a diode 110 is held at a prescribed voltage to turn on or off the JFET. Thus, a memory suitable to high integration and subminiaturization is obtained. |
