发明名称 DATA SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To eliminate the shift in edge timing due to the transfer characteristics of a signal transmission system, by performing synchronism through the extraction of only a falling edge in the timing permissible on signal format. CONSTITUTION:An input digital signal 1 is inputted to a falling edge detecting circuit 2, where a falling edge signal 3 is produced. The signal 3 clears a counting circuit 5. The circuit 5 counts a signal 4 other than the clear time and its output 6 is detected 7 to input a decode output 8 to an OR gate 20. The output of a gate 20 is latched to a latch circuit 10 in the timing of a signal 9, a latch output 11 and the signal 3 are made coincident at an AND gate 12 and a coincident output 13 is taken as a phase synchronizing signal to a start-stop type synchronizing circuit 15 to produce a data strobe pulse 16. An output 17 of the circuit 15 is decoded at a decoder 18, a decode output 19 is inputted to a gate 20 and an OR output 21 is inputted to the circuit 10. Thus, an abnormal edge is eliminated and a signal of the falling edge next to the abnormal edge passes through as the phase synchronizing signal.
申请公布号 JPS5864840(A) 申请公布日期 1983.04.18
申请号 JP19810162837 申请日期 1981.10.14
申请人 HITACHI SEISAKUSHO KK 发明人 ARAI TAKAO;OOKUBO EIJI;ENDOU HIROSHI;KOBAYASHI MASAHARU;TAKEUCHI TAKASHI
分类号 H04L7/02;H04L7/033;H04L7/04;H04L7/08 主分类号 H04L7/02
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