发明名称 SYNCHRONIZING CIRCUIT SYSTEM
摘要 <p>PURPOSE:To ensure a common use to both a subframe synchronizing circuit and a multiframe synchronizing circuit for a synchronism protecting circuit which is provided with several stages of counters and a latching circuit, by adding a selecting circuit including a logic element. CONSTITUTION:When a subframe synchronism is secured, the output of a subframe marker detecting circuit 101 is fed to the input terminals 7 and 8 of a coincidence circuit 402 and a discordance circuit 403 respectively via a selecting circuit 401. The subframe counter stopping signal is fed to a frame counter 201 from an output terminal 14 of a latching circuit 404 via the circuit 401. During this process, the subframe synchronism is secured. The multiframe synchronism is secured by switching the circuit 401.</p>
申请公布号 JPS5863246(A) 申请公布日期 1983.04.15
申请号 JP19810163027 申请日期 1981.10.13
申请人 NIPPON DENKI KK 发明人 SUGAWARA HIROYUKI;ROKUGOU YOSHINORI;ASANO HIROSHI
分类号 H04J3/06;H01J3/06;H04L7/08 主分类号 H04J3/06
代理机构 代理人
主权项
地址