| 摘要 |
PURPOSE:To compensate a delay by increasing signal charge quantity, and to obtain large signal voltage at a high speed, by placing a controlling circuit for cell plate voltage on a driving end part and a terminal part of a word line. CONSTITUTION:When a word line 5 selected by an X decoder 17 has been driven by a word line driver 18, as for a word line signal, rise of a terminal 5b is delayed against rise of a driving end 5a. In this case, voltage of a cell plate 8 is discharged, but this voltage waveform is also delayed. Discharge of a cell plate corresponding to a waveform whose rise is most delayed is quickened. Therefore, signal charge to a bit line 4 from a memory cell 1 is transferred at a high speed, and the delay of the word line signal is compensated. On the other hand, the cell plate 8 is charged by setting a signal phiG to a high level before the word line 5 is closed after write operation by a sense amplifying circuit. After that, the word line 5 is closed, and a data is inputted to the memory cell. As a result, the signal charge increases remarkably. |
