| 摘要 |
PURPOSE:To decrease the execution time of subroutine jump and return instruction, by incorporating an instruction address register and a register file for return address storage of a subroutine. CONSTITUTION:A jump instruction CALL is interpreted in a machine cycle T6, the jump address C is selected at a multiplexer 1 and a register REG2 is selected as an instruction address register with a control circuit 5A. Further, in a machine cycle T7, the register REG2 is revised by +1 at an addition/subtraction circuit 2, and when a return instruction RTN is interpreted in a machine cycle 8, the selection of the internal register of a register file 4 is changed from the register REG2 to a register REG1 with the control circuit 5A, control is transferred from the subroutine C to the subroutine B and the processing from the address B+3 to the subroutine B is restarted. |
