| 摘要 |
The output register (REG A...D) of the main or buffer memory (ASP, CA) is followed by a byte alignment displacement network (BART A...D), which aligns half-word memory operands with left alignment to byte (2 and 3) and longer memory operands in each case command-type-dependently to the left-hand or right-hand double-word boundary of the processor/memory interface. In addition, a bank selection/sign generator (BSVZG) following the byte alignment displacement network is provided which, in the case of half-word operands, replaces bytes 0 and 1 with sign bits and non-relevant bytes of half-word and memory operands by zeros. <IMAGE>
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