Halbleitervorrichtung

摘要

1276791 Semi-conductor devices TOKYO SHIBAURA ELECTRIC CO Ltd 21 Jan 1970 [22 Jan 1969 (2)] 2869/70 Heading H1K The figures illustrate representative embodiments of voltage-overload-protection devices (limiters) for use in integrated circuits and are here shown used to protect the gate circuits of IGFETS. Fig. 6 shows a substrate of one conductivity type in which are formed three zones of opposite conductivity type, two 78, 79 of which form the source and drain regions of an IGFET and the other of which 71 forms the body of the limiter. Two high conductivity regions 72, 73 of the same conductivity type as the substrate 77 complete the limiter. As shown the region 72 lies across the boundary between the zone 71 and the substrate. (The region 72 may be formed as an annular region to overlie the entire periphery.) In the variant of Fig. 7 one of the high conductivity regions 72 is an internal region. The design of the devices may be such that limiting is achieved by avalanche or Zener breakdown of that junction of the limiter which is reverse biased at the time or is achieved by punch-through between the two regions. The devices are designed to limit equally voltages of both polarities. In further variants, those high conductivity regions which lie in the major surface are replaced by Schottky barrier contacts.